In this paper we propose a fault simulation algorithm that utilizes all cores in multi-core processors. We adapt for multi-core workstation our early proposed distributed fault simulation algorithm. Proposed algorithm uses multi thread execution. The algorithm is based on the well-known "master-slave" approach in which one thread is nominated as a master and controls the calculation on all the other cores of processor. To maximize utilization of the cores a scheme with static fault list partitioning is used. The speed-up coefficient of the simulation time obtained during machine experiments is up to 3.44 times on the quad core system. Key words: digital circuit, sequential circuit, fault simulation, parallel simulation, multi-core processor, execution thread.
