FPGA-based realization of a digital recirculator meant for the ensuring digital spread spectrum signals synchronization in the communication systems with code division multiple access in the small ratio signal/noise conditions after the compression in the programmable digital matched filter (PDMF) is presented in this paper. Synthesized VHDL-model is presented in the RTL-level and is implemented in the FPGA ALTERA CYCLONE II EP2C70F672C6 using CAD QUARTUS. The ways of logic elements quantity reduction in the FPGA are proposed. Keywords: code division, FPGA, recirculator, synchronization, and digital
