The topic of my master thesis centred at verification of VHDL-codes that describe digital elements. It also covers the internal model of the verification object as composition of graph structures, which allow defining models of design errors, and the strategy of test generation for functional verification of a digital device description with usage of the description languages. This Strategy of verification of digital devices models, represented in hardware description languages, which is considered in this thesis explains the basic idea is in using path sensitization method in a graph model, generating distinguishing tests for separate functional elements, superposing these tests and interactive calculating etalon reactions. There is problem that we can encounter while simulation in order to check the correctness of the VHDL code, which is the problem of the input value that must be send to the simulation. Test generation method with functional approach which is also offered in this thesis. The main point of the method is decomposition of a digital device into so-called uniformly tested segments on a design stage. A method of test generation for one of segments type, namely for data-path (operational automaton), is developed. Test sequences for experimental objects are also obtained. Test generation features for functional testing using the updated algorithm of path activation in a structural model are described. The range method of data representation of different format data is introduced in this thesis, Algorithms for execution of direct implication and backtracing of different types of operations and their program realization are represented.
