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Ключові слова:
комплементарна логіка на транзисторах метал-окид-напівпровідник, КМОН, комплементарная логика на транзисторах металл-оксид-полупроводник,КМОП, CMOS-technology ; чисельне моделювання, численное моделирование ; моделювання, моделирование, modeling, simulation ; CMOS
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Анотація:
Negative Bias Temperature Instability (NBTI)-induced degradation for ultra-scaled and future-generation MOSFETs is investigated. Numerical simulations based on Reaction–Diffusion framework are implemented. Geometric dependence of degradation arising from the transistor structure and scaling is incorporated into the model. The simulations are applied to narrow-width planar triple-gate and surround-gate MOSFET geometries to estimate the NBTI reliability under several scaling scenarios. Unless the operating voltages are optimized for specific geometry of transistor cross section, the results imply worsened NBTI reliability for the future-generation devices based on the geometric interpretation of the NBTI degradation. A time-efficient and straightforward analysis is developed to predict the degradation. This compact model confirms the numerical simulations.
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